A Parallel Framework for Long-period Random Number Generators in Hardware

The accuracy of stochastic (Monte Carlo) simulations is critically dependent on the quality of their random number generator (RNG). Recently, such simulations are increasingly implemented in a parallel form on field-programmable gate arrays (FPGAs) for higher performance. Fast, high-quality RNGs with periods long enough for extended simulation (e.g., the Mersenne Twister) have been well-proven in software, but hardware implementations are rare. In this M.Sc. project, we develop an optimized framework for parallelizing long-period RNGs and implementing them on FPGAs. Both the underlying RNG algorithm as well as FPGA architectural aspects are exploited to provide a flexible trade-off between resource usage (area) and throughput. We also demonstrate three specific RNG implementations that are almost an order of magnitude faster than previous attempts and can significantly accelerate hardware Monte Carlo simulations. From an educational perspective, the project is an interesting blend of usually disjoint areas such as computer architecture, abstract algebra and applied probability. Some aspects of the project are currently being used in an undergraduate ‘system design’ course to introduce students with only basic knowledge of digital logic design and linear algebra to these advanced concepts via experimentation.